1. Field of the Invention
The invention is related to the field of electronic memory devices, and in particular, relates to a memory circuit design for reducing leakage power while maintaining timing performance.
2. Discussion of Related Art
In electronic memory devices, memory cells used for storing information are generally organized as a matrix of cells in column and row format. Memory cells which are organized in a specific row are coupled to a wordline signal path unique to the row. Memory cells which are organized along a specific column are coupled to a bitline signal path unique to the column. When the wordline on a row is activated, the memory cells arranged in the row become activated and allow information to be read from or written to the memory cells of that row along the bitlines in the columns.
In order to access information in the memory cells, memory devices typically use a row address to indicate which row of memory cells the information resides in. The row address is transmitted by control logic along a row address signal path to a plurality of identical row decode drivers, each of which is coupled to the row address signal path and to a corresponding wordline signal path coupled to a corresponding row. After receiving a row address, each row decode driver will determine if the row address identifies the particular row and the wordline signal path that the row decode driver is coupled to. If so, that row decode driver applies a signal to its corresponding wordline signal path to activate the memory cells of that corresponding row. When the row decode driver activates the wordline, memory cells along the wordline are selected for reading information from, or writing information to, the memory cells using the bitlines corresponding to the columns.
A timing delay (e.g., propagation delay and logic related delays) exists between transmitting the row address by the control logic, receiving the row address at any specific row decode driver, decoding the row address, and driving the wordline associated with the address. The rows of memory cells and the corresponding row decode driver circuits are physically placed on the memory circuit generally linearly displaced from the control logic that applies the row address to the row decode driver circuits. Thus a first row and its corresponding row decode driver may be physically closer to the control logic than the last row and its row decode driver circuit. The physical proximity of the row decode driver from the control logic affects the timing of the generation of wordline signals because of propagation delay differences between the various rows based on their proximity to the common control logic. When designing and specifying the memory device for timing, the “worst” case timing delay from the control logic to a row decode driver is determined and used for accessing information in the memory device. Use of the worst case timing ensures that under all conditions of accessing information in the memory device, regardless of the row being accessed, that the information will be valid.
Integrated circuit design always entails a tradeoff between speed of the circuit and leakage power. In general a circuit designed for higher speed operation will waste more power (e.g., leakage power) than will a similar circuit performing the same logic function at a slower clock speed. Thus it is an ongoing challenge in the design of memory devices to design for the required timing constraints (e.g., the worst case timing requirements of the row decode drivers coupled to the control logic) while reducing wasted leakage power.